I. (20 points) Consider the BCD-to-Seven-Segment Decoder design as discussed in the textbook (pages 30-31). Use K-maps to obtain a minimum SOP form for the output functions corresponding to Segment d and Segment g. Remember to exploit Don’t Care minterms 10 to 15. Label the K-maps exactly as shown in the book: X3 X2 for rows and X1 X0 for columns.
II. (30 points) Consider the following Boolean functions:
F1( A, B, C) = A . B + A’ . B. C ‘
F2( A, B, C ) = B . C ‘ + A. B’ . C + A . B
(i)
Implement F1 and F2 using one 3:8 Decoder module and two OR gates.
(ii)
Implement F1 and F2 using two 4:1 Multiplexers and one optional NOT gate.
(iii)
Implement F1 and F2 using a PLA that has 3 inputs, 2 outputs, and 4 products. Show the PLA logic using the notation as per Figure 1.35, page 44 of your text.
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